The demand for increasingly smaller devices has posed a number of challenges. One area in particular is memory devices including arrays of transistors including, for example, bipolar junction transistors (BJTs). The BJT arrays may include large numbers of individual memory cells, reducing the number of which is not typically an option due to the desire for increased memory capacity. Decoding and driving circuitry, usually located at the edges of the memory array, are generally necessary for accessing the memory cells of the memory array, but oftentimes consume a significant area of the overall size of the memory device.